The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, the approaches described in this section may not be prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In semiconductor integrated circuit manufacturing, it is conventional to test integrated circuits (“IC's”) during manufacturing and prior to shipment to ensure proper operation. Wafer testing is a well-known testing technique commonly used in production testing of wafer-mounted semiconductor IC's, wherein a temporary electrical connection is established between automatic test equipment (ATE) and each IC formed on the wafer to demonstrate proper performance of the IC's. Components that may be used in wafer testing include an ATE test board, which is a multilayer printed circuit board (PCB) that is connected to the ATE, and that transfers the test signals between the ATE and a probe card assembly. The probe test card assembly (or probe card) includes a PCB that generally contains several hundred probe needles (or “probes”) positioned to establish electrical contact with a series of connection terminals (or “die contacts”) on the IC wafer. Conventional probe card assemblies include a PCB, a substrate or probe head having a plurality of flexible test probes attached thereto, and a space transformer that electrically connects the probes to the PCB. The space transformer includes telescopic “spring pins” or solder bumps that provide electrical connections between conductive pads on the PCB and the space transformer and between the space transformer and conductive pads on the substrate. The test probes are conventionally mounted to electrically conductive, typically metallic, bonding pads on the substrate using solder attach, wire bonding or wedge bonding techniques.
The space transformer routs electrical contacts from very small pitches that typically exist on probe heads to a much larger pitch that is manufacturable for PCBs or other components in the assembly. While advances in silicon manufacturing technologies permit use of finer pitches, corresponding advances in existing space transformer technologies have failed to keep up, as more electrical contacts must fit in a smaller space. Thus as minimum pitch is reduced, manufacturing yield of space transformers is reduced, leading to higher costs.
Additionally, as parallel device testing techniques are incorporated into the manufacturing process, the increased number of interconnect contacts generates mechanical stress on the space transformer that could cause physical deformation of the space transformer past acceptable limits. The increased number of interconnect contacts in wired space transformers also leads to fragile wired space transformers which are more susceptible to damage and more cumbersome to repair.
Based on the foregoing, there is a need for a space transformer that does not suffer from limitations of conventional space transformers.